physnoct on JTAG-DP Sticky errors when pro…
Monthly Archives: December 2016
In my previous post, I ported the Multicomp from Grant Searle to an Altera Cyclone II FPGA platform. The Multicomp peripheral are quite minimal, and I wished to use the on board facilities. Code for these were supplied in Verilog. … Continue reading
I bought an Altera Cyclone FPGA RCQ208 development board (clone) on eBay a while ago. I ported the Multicomp project from Grant Searle for this platform.This is a minimal port: 1K internal RAM, a single UART, no video but support … Continue reading
This board does all the interconnect outside the bus connector. It has buffers to make ports 0x50 to 0x53 as tristate buffers. The circuit in the lower section converts ports 50-53 to hexadecimal for a VFD display.