In my previous post, I ported the Multicomp from Grant Searle to an Altera Cyclone II FPGA platform.
The Multicomp peripheral are quite minimal, and I wished to use the on board facilities. Code for these were supplied in Verilog. In my tiny pea brain, I figured that the geniuses at Altera could combine easily Verilog and VHDL code.
As soon as you add the Verilog file in the project, it’s recognized.
I ran into some errors; “design library work does not contain primary unit”. I tried different syntaxes and solutions found on the web without success, but after some tweaks, I succeeded in compiling the project.
Here is the working solution:
After including the Verilog file, we modify the main VHDL file to connect the new component.
library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity Microcomputer is port(-- all the ios, etc); end Microcomputer; architecture struct of Microcomputer is -- Here, we declare the Verilog component. -- This is a One Wire controller which is connected to a Dallas chip. component DS18B20_CTL is port(-- all the ios, etc); end component; begin -- We instanciate the Verilog component just as another VHDL component. ow1 : component DS18B20_CTL port map (-- all the ios, etc); -- Other VHDL code end;
It’s as simple as that!