Problem with assembler files when compiling a C project with SDCC and Codeblocks

I was trying to compile a simple C project (SDCC for Z80) with codeblocks. As usual, I stumble easily on minor problems, taking much time to look up for a solution. This time, it’s a small project that doesn’t want to compile.

Here is the code:


void putchar(char c);

void main(void)
 printf("Hello world\r\n");

void putchar(char c)
 call    0x0529

What could be simpler? When compiling the file, it generate these messages:

||=== Build: Release in test-vinc (compiler: SDCC Compiler) ===|
 obj/Release/main.asm|156|Error:  missing or improper operators, terminators, or delimiters|
 ||=== Build failed: 1 error(s), 0 warning(s) (0 minute(s), 0 second(s)) ===|

Of course, the project worked fine previously and there’s absolutely nothing wrong in my code. Here are my software versions:

Codeblocks 16.01
SDCC 3.3.2 #8942 (Feb 13 2014)

Well, the solution was simple.

To correct this problem, be sure to specify the particular CPU you’re using. In my case, Z80.

In CodeBlocks’ menu, select Project, Build options,


That’s it! Now it works!

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Altera Quartus, combining Verilog and VHDL

In my previous post, I ported the Multicomp from Grant Searle to an Altera Cyclone II FPGA platform.

The Multicomp peripheral are quite minimal, and I wished to use the on board facilities. Code for these were supplied in Verilog. In my tiny pea brain, I figured that the geniuses at Altera could combine easily Verilog and VHDL code.

As soon as you add the Verilog file in the project, it’s recognized.


I ran into some errors; “design library work does not contain primary unit”. I tried different syntaxes and solutions found on the web without success, but after some tweaks, I succeeded in compiling the project.

Here is the working solution:

After including the Verilog file, we modify the main VHDL file to connect the new component.

library ieee;
use ieee.std_logic_1164.all;

entity Microcomputer is
    port(-- all the ios, etc);
end Microcomputer;

architecture struct of Microcomputer is

-- Here, we declare the Verilog component.
-- This is a One Wire controller which is connected to a Dallas chip.
component DS18B20_CTL is
    port(-- all the ios, etc);
end component;


-- We instanciate the Verilog component just as another VHDL component.
ow1 : component DS18B20_CTL
port map (-- all the ios, etc);

-- Other VHDL code


It’s as simple as that!

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Z80 Basic computer on a FPGA

I bought an Altera Cyclone FPGA RCQ208 development board (clone) on eBay a while ago.


I ported the Multicomp project from Grant Searle for this platform.This is a minimal port: 1K internal RAM, a single UART, no video but support is possible for PS2 keyboard and SD card.

To make it work, follow the instructions on the multicomp webpage: it’s just a matter of cut and pasting the desired components into the file ‘multicomputer.vhd’. Then, with Quartus, you must change the device and change the pin assignation for your particular platform.

To change the device, on Quartus’ main menu, click assignments -> device and select EP2C8Q208Q; you will have to scrap the current assignations since the pins will not be at the same place as the original project.

To change the pin assignation, on the main menu, click assignments -> pin planner.

The result is this assignation for my FPGA board:

set_location_assignment PIN_14 -to rxd1
set_location_assignment PIN_15 -to txd1

set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to rxd1
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to rxd2

set_location_assignment PIN_23 -to clk
set_location_assignment PIN_27 -to n_reset

set_location_assignment PIN_207 -to ps2Data
set_location_assignment PIN_208 -to ps2Clk

set_location_assignment PIN_8 -to hSync
set_location_assignment PIN_10 -to vSync

set_location_assignment PIN_175 -to sdMISO
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sdMISO
set_location_assignment PIN_173 -to sdSCLK
set_location_assignment PIN_171 -to sdMOSI
set_location_assignment PIN_170 -to sdCS
set_location_assignment PIN_64 -to driveLED


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Z80 Monsputer interconnect

This board does all the interconnect outside the bus connector. It has buffers to make ports 0x50 to 0x53 as tristate buffers. The circuit in the lower section converts ports 50-53 to hexadecimal for a VFD display.


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Z80 Monsputer: CPU board

The Z80 Monsputer has of course a CPU. It went from several iterations of design over the years. This is probably not the last one because of the ugly patches.

  • Z80 CPU running at 4 MHz
  • 6850 main UART
  • 8253 for UART baud rate and buzzer sound
  • 6821 for use with the interconnect board
  • 8K EPROM or EEPROM for the BIOS
  • 6264 8K RAM with battery backup
  • 3 x 32k RAM
  • ATF1504AS CPLD for the glue logic

The CPLD chip isn’t big enough for the task, I had to put some ugly patches to make this work and this would need a redesign of this board to make it cleaner.




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Z80 Monsputer GPIO and vectored interrupts

This board is one of the first boards I’ve done for the monsputer. It has only TTL logic on it. I’ve probably made it about 25 years ago (or more!).

The chips came from a bunch of PCBs that I bought for $10 (Canadian). These were quite old and came from a 8-bit computer. The CPU was implemented with TTL logic. The ALU was made with 4 74S181.

The GPIO/Interrupts board has:

  • 8 x 8-bit inputs
  • 8 x 8-bit outputs
  • 8 vectored interrupt inputs


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Z80 Monsputer memory card

This board has:

  • 512k dynamic RAM
  • 4 x 256k EPROM
  • 2 x 128k FLASH
  • 2 x 32k SRAM
  • CPLD for glue logic

The CPLD generates all the signals for refreshing the dynamic RAM. It also generates an 8th bit address for the memory refresh.


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