I bought an Altera Cyclone FPGA RCQ208 development board (clone) on eBay a while ago.
I ported the Multicomp project from Grant Searle for this platform.This is a minimal port: 1K internal RAM, a single UART, no video but support is possible for PS2 keyboard and SD card.
To make it work, follow the instructions on the multicomp webpage: it’s just a matter of cut and pasting the desired components into the file ‘multicomputer.vhd’. Then, with Quartus, you must change the device and change the pin assignation for your particular platform.
To change the device, on Quartus’ main menu, click assignments -> device and select EP2C8Q208Q; you will have to scrap the current assignations since the pins will not be at the same place as the original project.
To change the pin assignation, on the main menu, click assignments -> pin planner.
The result is this assignation for my FPGA board:
set_location_assignment PIN_14 -to rxd1
set_location_assignment PIN_15 -to txd1
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to rxd1
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to rxd2
set_location_assignment PIN_23 -to clk
set_location_assignment PIN_27 -to n_reset
set_location_assignment PIN_207 -to ps2Data
set_location_assignment PIN_208 -to ps2Clk
set_location_assignment PIN_8 -to hSync
set_location_assignment PIN_10 -to vSync
set_location_assignment PIN_175 -to sdMISO
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sdMISO
set_location_assignment PIN_173 -to sdSCLK
set_location_assignment PIN_171 -to sdMOSI
set_location_assignment PIN_170 -to sdCS
set_location_assignment PIN_64 -to driveLED
This board does all the interconnect outside the bus connector. It has buffers to make ports 0x50 to 0x53 as tristate buffers. The circuit in the lower section converts ports 50-53 to hexadecimal for a VFD display.
The Z80 Monsputer has of course a CPU. It went from several iterations of design over the years. This is probably not the last one because of the ugly patches.
- Z80 CPU running at 4 MHz
- 6850 main UART
- 8253 for UART baud rate and buzzer sound
- 6821 for use with the interconnect board
- 8K EPROM or EEPROM for the BIOS
- 6264 8K RAM with battery backup
- 3 x 32k RAM
- ATF1504AS CPLD for the glue logic
The CPLD chip isn’t big enough for the task, I had to put some ugly patches to make this work and this would need a redesign of this board to make it cleaner.
This board is one of the first boards I’ve done for the monsputer. It has only TTL logic on it. I’ve probably made it about 25 years ago (or more!).
The chips came from a bunch of PCBs that I bought for $10 (Canadian). These were quite old and came from a 8-bit computer. The CPU was implemented with TTL logic. The ALU was made with 4 74S181.
The GPIO/Interrupts board has:
- 8 x 8-bit inputs
- 8 x 8-bit outputs
- 8 vectored interrupt inputs
This board has:
- 512k dynamic RAM
- 4 x 256k EPROM
- 2 x 128k FLASH
- 2 x 32k SRAM
- CPLD for glue logic
The CPLD generates all the signals for refreshing the dynamic RAM. It also generates an 8th bit address for the memory refresh.
This card has several protocols:
- CAN (SJA1000)
- I²C (PCF8584)
- Serial (16550,6852)
- Parallel Port (CPLD)
- SPI (CPLD)
- External ports
There are 2 CPLDs:
- ATF1504 parallel port
- ATF1508 SPI,vectored interrupts 10-1F, glue logic
Here’s a look of the other side: I use very fine magnet wire for all signals and bigger ones for power.
A board that I made previously took too much glue logic and a multiplexing circuit was not working well enough so I decided to redo this board.
- 2 x 6850 UARTs with 8253 counter for baud rates
- 6840 Timer/Counter
- Dallas DS1501Y RTC
- 68A21 PIO
- 8255 PIO
- AD7824 4-channel ADC
- DAC08 8-bit DAC
- ATF1504 84-pin CPLD for SPI and glue logic
The eagle schematic and CPLD file are available at Sourceforge: