Nobody saw this coming

Nobody saw this coming.

I don’t know how all of this began and when. Trump was reelected with a surprising majority. Or maybe before, when flat earthers reemerged on the web, proclaiming the earth is flat, based on old unscientific books written long before modern science.

Or how the internet web was beginning to have shitty content of people mutilating themselves or attempting to do all sorts of crazy stuff. You may not know this, reader in the future, but the internet allowed us to share almost everything on cyberspace. It allowed all the computers of the whole planet to communicate with all others. And I’m not even talking about the dark web. Who knows what’s on this and I don’t even want to know. Considering the horrific things we get in the news, one can only think that there must be horrifying stuff beyond imagination. Anyway, enough of that.

There was also all that craze about the zombie apocalypse, but of course, it’s just fiction. There was a tremendous increase of violence everywhere. The radical islamists, the numerous shootings in the United-States, etc. The web was regularly predicting the end of the world each year without success, fortunately. The 4 Blood Moons (just a natural phenomenon), the Rapture (it never happened), the Angel Trumpets (fakes). There was so much conspiracies everywhere that nothing seemed believable anymore. Nasa, Moon landings, ISS, pictures from space, and so many more.
It may not be surprising that if the USA was a culture of fakes, US citizens grew tired of all this fakery. YouTube was merely a vent for all those frustrations.

Many virus appeared after the AIDS virus. Fortunately, with modern science, medicine could annihilate even AIDS. But this …

But all that was nothing, compared to that thing. Nobody knows what it is exactly, but it must not touch you in any way or you’re done (I don’t know for sure). The best comparison I can say is that it’s as if a hacker exploited all the biological backdoors of your body. It may rot you, or transform you into a zombie, or whatever else. Yet, I’m not sure, it’s still matter of speculations. We don’t know all the possible vectors of propagation of that horrible thing.
I don’t know how it looks like. The only thing I know is that your instinct kicks in and you have a feeling there is something horribly wrong going on. Pretty much like the suspense music when there is something about to happen.

I don’t know how this will end and if the readers in the future will even be humajkhlkgjjhvm   hgljgjhg    helpjgjklgjkghjkg     oi;lkj;ljlj            fdgsfsa54……………………………….

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Spinning ball model

If we were to reproduce a spinning ball holding water, we should have gravitation exceeding the centrifugal acceleration (300 times stronger normally).

The gravity (acceleration) holding the water should be: g = Gm1/R².

Since we will scale down the model, we will need to know the limit to where we can go.
We need to convert m1/R² to use density:

density = mass/volume -> mass = density * volume.
volume of a sphere = 4πr³/3
m1/R² = d1 * 4πR³/3R² = d1 * 4πR/3 where d1 is the earth’s density (5.51g/cm³)

On earth and the scale model, the gravity is g = Gm1/R² = 4πGRd1/3

We can see here that the gravity at “sea” level is proportional to the radius (other values are constants) hence g = kR where k = 4πGd1/3

The centrifugal acceleration is also proportional to the radius: α = ω²r

To not fling everything in space we need to have g ≥ α, or kR ≥ ω²R or k ≥ ω²

So the rotational speed limit doesn’t depend on the radius. This means that we can make a model small enough for experiments.

The limit for the rotational speed is 1.24 mrad/s which is 17 revolutions per day.

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Problem with assembler files when compiling a C project with SDCC and Codeblocks

I was trying to compile a simple C project (SDCC for Z80) with codeblocks. As usual, I stumble easily on minor problems, taking much time to look up for a solution. This time, it’s a small project that doesn’t want to compile.

Here is the code:

#include

void putchar(char c);


void main(void)
 {
 printf("Hello world\r\n");
 }

void putchar(char c)
 {
 c;
 __asm
 call    0x0529
 __endasm;
 }

What could be simpler? When compiling the file, it generate these messages:

||=== Build: Release in test-vinc (compiler: SDCC Compiler) ===|
 obj/Release/main.asm|156|Error:  missing or improper operators, terminators, or delimiters|
 ||=== Build failed: 1 error(s), 0 warning(s) (0 minute(s), 0 second(s)) ===|

Of course, the project worked fine previously and there’s absolutely nothing wrong in my code. Here are my software versions:

Codeblocks 16.01
SDCC 3.3.2 #8942 (Feb 13 2014)

Well, the solution was simple.

To correct this problem, be sure to specify the particular CPU you’re using. In my case, Z80.

In CodeBlocks’ menu, select Project, Build options,

sdcc-cpu

That’s it! Now it works!

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Altera Quartus, combining Verilog and VHDL

In my previous post, I ported the Multicomp from Grant Searle to an Altera Cyclone II FPGA platform.

The Multicomp peripheral are quite minimal, and I wished to use the on board facilities. Code for these were supplied in Verilog. In my tiny pea brain, I figured that the geniuses at Altera could combine easily Verilog and VHDL code.

As soon as you add the Verilog file in the project, it’s recognized.

verilog

I ran into some errors; “design library work does not contain primary unit”. I tried different syntaxes and solutions found on the web without success, but after some tweaks, I succeeded in compiling the project.

Here is the working solution:

After including the Verilog file, we modify the main VHDL file to connect the new component.

library ieee;
use ieee.std_logic_1164.all;
use  IEEE.STD_LOGIC_ARITH.all;
use  IEEE.STD_LOGIC_UNSIGNED.all;

entity Microcomputer is
    port(-- all the ios, etc);
end Microcomputer;

architecture struct of Microcomputer is

-- Here, we declare the Verilog component.
-- This is a One Wire controller which is connected to a Dallas chip.
component DS18B20_CTL is
    port(-- all the ios, etc);
end component;

begin

-- We instanciate the Verilog component just as another VHDL component.
ow1 : component DS18B20_CTL
port map (-- all the ios, etc);

-- Other VHDL code

end;

It’s as simple as that!

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Z80 Basic computer on a FPGA

I bought an Altera Cyclone FPGA RCQ208 development board (clone) on eBay a while ago.

dscn0374

I ported the Multicomp project from Grant Searle for this platform.This is a minimal port: 1K internal RAM, a single UART, no video but support is possible for PS2 keyboard and SD card.

To make it work, follow the instructions on the multicomp webpage: it’s just a matter of cut and pasting the desired components into the file ‘multicomputer.vhd’. Then, with Quartus, you must change the device and change the pin assignation for your particular platform.

To change the device, on Quartus’ main menu, click assignments -> device and select EP2C8Q208Q; you will have to scrap the current assignations since the pins will not be at the same place as the original project.

To change the pin assignation, on the main menu, click assignments -> pin planner.

The result is this assignation for my FPGA board:

set_location_assignment PIN_14 -to rxd1
set_location_assignment PIN_15 -to txd1


set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to rxd1
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to rxd2

set_location_assignment PIN_23 -to clk
set_location_assignment PIN_27 -to n_reset


set_location_assignment PIN_207 -to ps2Data
set_location_assignment PIN_208 -to ps2Clk

set_location_assignment PIN_8 -to hSync
set_location_assignment PIN_10 -to vSync

set_location_assignment PIN_175 -to sdMISO
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sdMISO
set_location_assignment PIN_173 -to sdSCLK
set_location_assignment PIN_171 -to sdMOSI
set_location_assignment PIN_170 -to sdCS
set_location_assignment PIN_64 -to driveLED

 

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Z80 Monsputer interconnect

This board does all the interconnect outside the bus connector. It has buffers to make ports 0x50 to 0x53 as tristate buffers. The circuit in the lower section converts ports 50-53 to hexadecimal for a VFD display.

dscn0366

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Z80 Monsputer: CPU board

The Z80 Monsputer has of course a CPU. It went from several iterations of design over the years. This is probably not the last one because of the ugly patches.

  • Z80 CPU running at 4 MHz
  • 6850 main UART
  • 8253 for UART baud rate and buzzer sound
  • 6821 for use with the interconnect board
  • 8K EPROM or EEPROM for the BIOS
  • 6264 8K RAM with battery backup
  • 3 x 32k RAM
  • ATF1504AS CPLD for the glue logic

The CPLD chip isn’t big enough for the task, I had to put some ugly patches to make this work and this would need a redesign of this board to make it cleaner.

DSCN0360.JPG

 

 

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